I'm designing an HDL language to make FPGAs easier to use for makers and hobbyists. Please take a look at this simple example and provide your own ideas and feedback. Retweet or forward for greater exposure.https://gist.github.com/tinyfpga/a646c8681166188fc7769d80d425e876 …
No more inefficient than "mul by an arbitrary constant" can be. Maybe you think div encourages bad idioms but mul doesn't and maybe that's correct.
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Nope, DIV is just hard - eg. Intel Skylake, 64-bit IDIV = 64 to 95 cycles vs 64-bit IMUL 3 cycles. That is why even GCC tries to avoid division by substituting bit-fiddling tricks.
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No, that's div by variable which is completely different in complexity from div by constant.
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So we agree? - Division by a power of two is trivial - Division by a constant can be substituted with multiplication + correction step - Division by a 'variable' is hard Last two are not well-suited to FPGAs. They requires a lot of cycles/resources to get the accuracy.
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I'll agree to that with the caveat that *exact* division by a variable is hard. In DSP we can often tolerate some error / noise and so an inverse LUT coupled with a multiplier is often sufficient and quite fast for hardware implementations.
End of conversation
New conversation -
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