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RichFelker's profile
Rich Felker
Rich Felker
Rich Felker
@RichFelker

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Rich Felker

@RichFelker

Yeah, I do @musllibc, FOSS & infosec stuff. But now is not the time for a mostly-/only-tech Twitter feed.

musl-libc.org
Joined March 2014

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    1. Luke Valenty‏ @TinyFPGA Jan 21

      I'm designing an HDL language to make FPGAs easier to use for makers and hobbyists. Please take a look at this simple example and provide your own ideas and feedback. Retweet or forward for greater exposure.https://gist.github.com/tinyfpga/a646c8681166188fc7769d80d425e876 …

      19 replies 46 retweets 91 likes
      Show this thread
    2. Michael Field‏ @field_hamster Jan 22
      Replying to @TinyFPGA

      Outlaw division. The H/W & time cost of the "/" is underestimated by S/W coders. e,g: for(i = 0; i < 7; i++) total += value[i]; output = total/7; Do you stall the pipeline to do the division, or do you chew through resources?

      1 reply 1 retweet 2 likes
      Rich Felker‏ @RichFelker Jan 22
      Replying to @field_hamster @ico_TC @TinyFPGA

      Then outlaw mul too, because div by constant is basically just a mul with some bits thrown away...

      1:02 PM - 22 Jan 2018
      1 reply 0 retweets 0 likes
        1. New conversation
        2. Michael Field‏ @field_hamster Jan 22
          Replying to @RichFelker @ico_TC @TinyFPGA

          At least MUL can be decomposed to be done efficiently: output = (total<<2) + (total<<1) +total; Requires two adders, single cycle as bit-shifts come free in FPGA) Now try that with division by 7.

          1 reply 1 retweet 1 like
        3. Rich Felker‏ @RichFelker Jan 22
          Replying to @field_hamster @ico_TC @TinyFPGA

          It's a mul by 0x24924925 and some minor fixups. Obviously more expensive than a mul by 7 but not than a mul by 0x24924925.

          1 reply 0 retweets 0 likes
        4. Michael Field‏ @field_hamster Jan 22
          Replying to @RichFelker @ico_TC @TinyFPGA

          Um? 1/7 = 0 1*0x24924925 = 0x24924925 (Just being a pain - but it does point out that to do a 32 bit divide that way you need 64-bit intermediate results.

          1 reply 1 retweet 2 likes
        5. Rich Felker‏ @RichFelker Jan 22
          Replying to @field_hamster @ico_TC @TinyFPGA

          Of course. You throw away the low 32 bits of the result.

          1 reply 0 retweets 1 like
        6. Michael Field‏ @field_hamster Jan 22
          Replying to @RichFelker @ico_TC @TinyFPGA

          And then you still get 613,566,756 errors over the full range of 32-bit unsigned values, starting with 101,431,655,770, which gives 204522253 vs 204522252) CAUTION: been here before, felt the pain :)pic.twitter.com/FMSEc25woU

          1 reply 0 retweets 0 likes
        7. Rich Felker‏ @RichFelker Jan 22
          Replying to @field_hamster @ico_TC @TinyFPGA

          There's a tiny fixup you need for zero errors. The procedure for generating these is well-documented & has correctness proofs. GCC uses it.

          1 reply 0 retweets 0 likes
        8. Michael Field‏ @field_hamster Jan 22
          Replying to @RichFelker @ico_TC @TinyFPGA

          Sure, but does it translate into an efficient H/W implementation, vs taking the care to avoid the need for division in the first place?

          1 reply 0 retweets 0 likes
        9. Rich Felker‏ @RichFelker Jan 22
          Replying to @field_hamster @ico_TC @TinyFPGA

          No more inefficient than "mul by an arbitrary constant" can be. Maybe you think div encourages bad idioms but mul doesn't and maybe that's correct.

          1 reply 0 retweets 0 likes
        10. 4 more replies

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