I'm designing an HDL language to make FPGAs easier to use for makers and hobbyists. Please take a look at this simple example and provide your own ideas and feedback. Retweet or forward for greater exposure.https://gist.github.com/tinyfpga/a646c8681166188fc7769d80d425e876 …
Then outlaw mul too, because div by constant is basically just a mul with some bits thrown away...
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At least MUL can be decomposed to be done efficiently: output = (total<<2) + (total<<1) +total; Requires two adders, single cycle as bit-shifts come free in FPGA) Now try that with division by 7.
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It's a mul by 0x24924925 and some minor fixups. Obviously more expensive than a mul by 7 but not than a mul by 0x24924925.
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Um? 1/7 = 0 1*0x24924925 = 0x24924925 (Just being a pain - but it does point out that to do a 32 bit divide that way you need 64-bit intermediate results.
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Of course. You throw away the low 32 bits of the result.
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And then you still get 613,566,756 errors over the full range of 32-bit unsigned values, starting with 101,431,655,770, which gives 204522253 vs 204522252) CAUTION: been here before, felt the pain :)pic.twitter.com/FMSEc25woU
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There's a tiny fixup you need for zero errors. The procedure for generating these is well-documented & has correctness proofs. GCC uses it.
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Sure, but does it translate into an efficient H/W implementation, vs taking the care to avoid the need for division in the first place?
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No more inefficient than "mul by an arbitrary constant" can be. Maybe you think div encourages bad idioms but mul doesn't and maybe that's correct.
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