so, status as-of last night: early experimental BJX1 core synthesizes, uses ~11 kLUT (8k w/o FPU), but as-is fails timing at 100MHz, 75MHz works for int core; FPU still needs work here. not too terrible for a "stage 0" prototype...
Failing to meet timing doesn't necessarily mean it won't work, just that the tools aren't able to claim it works.
-
-
yep. still going to fiddle with it, see if I can make everything pass, but as-is it is possible some ops may need to use multiple clock cycles though (as-is, it looks likely for MUL*/DMUL*, and for the FPU ops and similar).
Thanks. Twitter will use this to make your timeline better. UndoUndo
-
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.