A more technical writeup on what can be done to address #Meltdown and #Spectre in future CPU designs. If there's interest, I can write a longer version with graphics and so on:https://www.linkedin.com/pulse/addressing-meltdown-spectre-future-silicon-jon-masters/ …
There's no universal sw fix. It requires hacks everywhere that might be affected. That's not viable (many will be missed) much less sustainable.
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Right - it’s a compiler level thing or you just have hacks. And I agree. But the big hammer isn’t going to be viable so we *will* have hacks
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No, it's a kernel-level thing or you just have hacks. Inability to safely run existing binaries for the baseline ISA means you're effectively not compatible with the original ISA/ABI... in which case, why stick with x86 at all?
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I agree we *will* have hacks for the forseeable future, but the hacks will be partial mitigations for safety in existing broken chips. New chips need full safety against Spectre variant 1.
End of conversation
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Disabling speculative reads from an address computed with a dependency on a speculative load is a big hammer that should fix it, but something lighter is needed to meet most users' performance requirements. (I'd be happy using an option to disable them, tho.)
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There should be a solution based on special handling of speculative loads that would cause cache miss (not fetching speculatively, but also hiding whether they did).
End of conversation
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