"I should note that we kernel programmers have spent decades trying to reduce system call overheads, so to be sure, we are all pretty pissed off at Intel right now."https://twitter.com/_xhr_/status/949402265680478208 …
-
-
AFAICT: one downside of the register banking is that, as designed, it is only really usable for ISRs. operating in the alternate bank in kernel space would come at the cost of being unable to handle ISRs. would instead need 4 banks or something (eg: user, kernel, ISR, uCode).
-
There are lots of good approaches that don't hit this problem. Allowing async interruption of kernel is a bad idea.
-
ok, depends probably on how the kernel handles hardware IRQ's or similar.
End of conversation
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.