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RichFelker's profile
Rich Felker
Rich Felker
Rich Felker
@RichFelker

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Rich Felker

@RichFelker

Yeah, I do @musllibc, FOSS & infosec stuff. But now is not the time for a mostly-/only-tech Twitter feed.

musl-libc.org
Joined March 2014

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    1. Bryan Steele‏ @canadianbryan Jan 6

      Bryan Steele Retweeted Matthias (@_xhr_@mastodon.social)

      "I should note that we kernel programmers have spent decades trying to reduce system call overheads, so to be sure, we are all pretty pissed off at Intel right now."https://twitter.com/_xhr_/status/949402265680478208 …

      Bryan Steele added,

      Matthias (@_xhr_@mastodon.social) @_xhr_
      Matt Dlllon just committed a Meltdown mitigation to #DragonFlyBSD http://lists.dragonflybsd.org/pipermail/users/2018-January/313758.html …
      2 replies 53 retweets 93 likes
    2. Rich Felker‏ @RichFelker Jan 6
      Replying to @canadianbryan

      Fastest syscall: pin half your cores to kernel syscall handler, spin on both sides (kernel & user) for the call/ret.

      1 reply 1 retweet 1 like
    3. Jonas Termansen‏ @sortiecat Jan 6
      Replying to @RichFelker @canadianbryan

      Has this been done? It could be fun to experiment with such a design.

      1 reply 0 retweets 0 likes
    4. Rich Felker‏ @RichFelker Jan 6
      Replying to @sortiecat @canadianbryan

      Really nice would be cpu-level support: extra register file like HT but not extra execution pipeline. Syscall price = nothing but pipeline flush.

      2 replies 0 retweets 0 likes
      Rich Felker‏ @RichFelker Jan 6
      Replying to @RichFelker @sortiecat @canadianbryan

      But then kernel would have to be aware that syscalls are not rescheduling opportunities without additional work.

      8:11 AM - 6 Jan 2018
      1 reply 0 retweets 0 likes
        1. New conversation
        2. Rich Felker‏ @RichFelker Jan 6
          Replying to @RichFelker @sortiecat @canadianbryan

          SH4 has a register banking feature something like this, probably other archs too. But Linux doesn't use it. Just saves the other bank to sigcontext on kernel entry.

          1 reply 0 retweets 1 like
        3. Brendan G Bohannon‏ @cr88192 Jan 6
          Replying to @RichFelker @sortiecat @canadianbryan

          AFAICT: one downside of the register banking is that, as designed, it is only really usable for ISRs. operating in the alternate bank in kernel space would come at the cost of being unable to handle ISRs. would instead need 4 banks or something (eg: user, kernel, ISR, uCode).

          1 reply 0 retweets 0 likes
        4. Rich Felker‏ @RichFelker Jan 6
          Replying to @cr88192 @sortiecat @canadianbryan

          There are lots of good approaches that don't hit this problem. Allowing async interruption of kernel is a bad idea.

          1 reply 0 retweets 0 likes
        5. Brendan G Bohannon‏ @cr88192 Jan 6
          Replying to @RichFelker @sortiecat @canadianbryan

          ok, depends probably on how the kernel handles hardware IRQ's or similar.

          0 replies 0 retweets 0 likes
        6. End of conversation

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