"I should note that we kernel programmers have spent decades trying to reduce system call overheads, so to be sure, we are all pretty pissed off at Intel right now."https://twitter.com/_xhr_/status/949402265680478208 …
Really nice would be cpu-level support: extra register file like HT but not extra execution pipeline. Syscall price = nothing but pipeline flush.
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But then kernel would have to be aware that syscalls are not rescheduling opportunities without additional work.
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SH4 has a register banking feature something like this, probably other archs too. But Linux doesn't use it. Just saves the other bank to sigcontext on kernel entry.
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AFAICT: one downside of the register banking is that, as designed, it is only really usable for ISRs. operating in the alternate bank in kernel space would come at the cost of being unable to handle ISRs. would instead need 4 banks or something (eg: user, kernel, ISR, uCode).
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There are lots of good approaches that don't hit this problem. Allowing async interruption of kernel is a bad idea.
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ok, depends probably on how the kernel handles hardware IRQ's or similar.
End of conversation
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banking register files gets you... basically nothing. The overhead of saving registers is noise.
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