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RichFelker's profile
Rich Felker
Rich Felker
Rich Felker
@RichFelker

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Rich Felker

@RichFelker

Yeah, I do @musllibc, FOSS & infosec stuff. But now is not the time for a mostly-/only-tech Twitter feed.

musl-libc.org
Joined March 2014

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    1. Rich Felker‏ @RichFelker Jan 3

      Proposed fix to protect the kernel from Spectre (& Meltdown).pic.twitter.com/qQZr4Iw2yw

      3 replies 2 retweets 9 likes
      Show this thread
    2. William Pitcock‏ @nenolod Jan 3
      Replying to @RichFelker

      actually I like that idea, and it should be possible with MTRRs. i like that way better than PTI.

      1 reply 0 retweets 0 likes
    3. Rich Felker‏ @RichFelker Jan 3
      Replying to @nenolod

      You realize it would run at about the speed of a 386, right? With the turbo button turned off.

      2 replies 0 retweets 1 like
    4. William Pitcock‏ @nenolod Jan 3
      Replying to @RichFelker

      no, you use MTRRs to restrict which mappings are cacheable depending on user or kernel context, then do a CLFLUSH when entering/exiting kernel

      1 reply 0 retweets 0 likes
      Rich Felker‏ @RichFelker Jan 3
      Replying to @nenolod

      MTRRs are for physical ranges, not virtual, no? But yes just flushing cache on kernel enter/return would work if you disable HT.

      7:41 PM - 3 Jan 2018
      1 reply 0 retweets 0 likes
        1. New conversation
        2. William Pitcock‏ @nenolod Jan 3
          Replying to @RichFelker

          yes, physical, but the memory manager can handle the details. using PATs would be even more flexible

          1 reply 0 retweets 0 likes
        3. Rich Felker‏ @RichFelker Jan 3
          Replying to @nenolod

          It really can't. That completely breaks logical layering and makes it hopelessly complex and therefore bug-ridden. And it probably exceeds limit on # of MTRRs.

          1 reply 0 retweets 0 likes
        4. William Pitcock‏ @nenolod Jan 3
          Replying to @RichFelker

          honestly CLFLUSH would probably be "good enough" if we could CLFLUSH the sibling threads (on the same physical core) too. i wonder if there is a way to synchronize sysenter/sysexit in this way using the topology data we already have

          1 reply 0 retweets 0 likes
        5. Rich Felker‏ @RichFelker Jan 3
          Replying to @nenolod

          As long as HT is there, attacker will have opportunities to observe cache effects. Exploit runs on both threads, synchronizing via shared mem spinlocks, executes syscall on one while probing cache from other.

          0 replies 0 retweets 0 likes
        6. End of conversation

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