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RichFelker's profile
Rich Felker
Rich Felker
Rich Felker
@RichFelker

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Rich Felker

@RichFelker

Yeah, I do @musllibc, FOSS & infosec stuff. But now is not the time for a mostly-/only-tech Twitter feed.

musl-libc.org
Joined March 2014

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    1. Dougall‏ @dougallj Jan 2

      Yes - Intel does have broken speculative execution, @scarybeasts (not an arbitrary read yet, but definitely a leak that shouldn't work)pic.twitter.com/qx2dcJsjzB

      4 replies 94 retweets 160 likes
      Show this thread
    2. Dougall‏ @dougallj Jan 3

      I just read @anders_fogh's https://cyber.wtf/2017/07/28/negative-result-reading-kernel-memory-from-user-mode/ … - it's very close, but I found testing assumptions 1, 2 and 3 sequentially in reverse order to be practical. Loading caches during speculative execution gave me 1 bit of output, which I used to verify the rest.

      2 replies 12 retweets 21 likes
      Show this thread
    3. Dougall‏ @dougallj Jan 3

      I can read user memory using speculative exec reliably. Page faults halt speculative execution reliably. Loads from kernel memory show up as zero, but not reliably. Certain addresses (eg those shown above), return data some percent of the time. Next step is finding out which/why.

      2 replies 12 retweets 20 likes
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    4. Dougall‏ @dougallj Jan 3

      Probability looks the same in 64 byte blocks, implying cache lines. Theory: permission check happens when the memory isn't in some cache. If the permission check passes, it's brought into L1 (so user memory always works), otherwise the caches stay the same and it uses zero.

      1 reply 3 retweets 11 likes
      Show this thread
    5. Dougall‏ @dougallj Jan 3

      It's hard to get clear data, as probabilities change over time. But if that's right, I'll need an instruction or trick to get arbitrary kernel memory into L1 (prefetch instructions don't seem to work). I may write a kernel module to test the theory.

      1 reply 2 retweets 12 likes
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      Rich Felker‏ @RichFelker Jan 3
      Replying to @dougallj

      If this is truely the issue, kernel could mitigate by flushing L1 before returning rather than costly page table switches.

      6:11 AM - 3 Jan 2018
      • 1 Like
      • Jonas Termansen
      1 reply 0 retweets 1 like
        1. New conversation
        2. Dougall‏ @dougallj Jan 3
          Replying to @RichFelker

          That's a really interesting point - I assume between the multiple kernel teams they've considered this, so maybe my theory is false, or maybe there's a trick to load kernel data into L1 without context switching? (A hyper-thread on the same core?)

          1 reply 0 retweets 2 likes
        3. Anil Kurmus‏ @kurmus Jan 3
          Replying to @dougallj @RichFelker

          I think that the latter is correct - I was also thinking about the L1$ flush mitigation, but HT thread should be able to force-populate L1 w/ kernel data indeed.

          1 reply 0 retweets 1 like
        4. Rich Felker‏ @RichFelker Jan 3
          Replying to @kurmus @dougallj

          Indeed, but for many workloads I'd happily choose disabling HT over making syscalls 2-5x as costly.

          0 replies 0 retweets 1 like
        5. End of conversation

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