Jokes aside, closest you'll probably come is implementing a bytecode interpreter to make it implausible for uarch to make op times vary.
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Honestly your average interpreter is probably going to leak gobs of secret information into the branch predictor. this is a terrible idea.
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No branching needed.
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Replying to @RichFelker @erincandescent and
You forget that add (with pc as a possible operand) is Turing complete. :-)
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So instead you’re leaking into the caches and ITLB, since they’re now functioning as your branch predictor =)
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Replying to @stephentyrone @RichFelker and
(Also, add-to-PC is a branch that can be predicted)
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Not host pc. Virtual machine pc.
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Yeah, in that case see previous comment. The caches hold your branch history.
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But you also write your code that runs in the vm such that its branch history is worthless.
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in that case why do you have the vm?
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To mitigate variable insn timing (if you can write host asm) or lack of timing model in C (portable code only).
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