Not a big problem when writing from scratch. Massive goddamn pain in the ass when trying to patch hand-written asm designed to use everything available.
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Replying to @stephentyrone @oshepherd and
Could be worse though, could be Cortex-M0 asm.
1 reply 0 retweets 0 likes -
Replying to @stephentyrone @hikari_no_yume and
...That is Thumb-1 (its a complete superset of the usermode ARMv4T instructions)
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Replying to @erincandescent @oshepherd and
Yeah, you’re right. For some reason I was misremembering having CLZ. Ugh, bad memories.
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Replying to @stephentyrone @oshepherd and
(FFS people, when you design an ISA, put CLZ in. The fact that you never see it in high-level languages does not mean it’s not necessary.)
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Replying to @stephentyrone @oshepherd and
Someone really needs to publish a paper that’s just a list of bad ISA and ABI decisions and why they’re bad and what to do instead.
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Replying to @stephentyrone @hikari_no_yume and
Starting point: * Your ISA should have [R+R<<k] loads/stores * An instruction which can compute A=B+C<<k is incredibly useful * 20-bit branch range is not enough (look at the size of a chromium lib sometime) * Have something like A64 BFM or PPC RLWINM
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Replying to @erincandescent @oshepherd and
Some starter notes for the ABI side: - do not pass FP values in GPR. When you’re bringing up a new arch, you’ll benchmark the math library and think this is a good idea. It isn’t. The math library is not at all like other FP code.
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Replying to @stephentyrone @oshepherd and
- do not place struct return pointers or va_args counts in one of the normal param registers. You want to have a single map from parameter types and positions to registers / memory.
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Replying to @stephentyrone @oshepherd and
can we say "do not put va_args parameters in registers"
2 replies 0 retweets 1 like
This pessimizes certain mildly variadic functions like open(2).
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