Writing Thumb-1 by hand is an exercise in frustration of the "Ugh, I can only use lo registers here. Ugh, this instruction only comes in a flag setting variant" variety
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Replying to @erincandescent @oshepherd and
Been there done that got the postcard.
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Replying to @stephentyrone @oshepherd and
Not a big problem when writing from scratch. Massive goddamn pain in the ass when trying to patch hand-written asm designed to use everything available.
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Replying to @stephentyrone @oshepherd and
Could be worse though, could be Cortex-M0 asm.
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Replying to @stephentyrone @hikari_no_yume and
...That is Thumb-1 (its a complete superset of the usermode ARMv4T instructions)
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Replying to @erincandescent @oshepherd and
Yeah, you’re right. For some reason I was misremembering having CLZ. Ugh, bad memories.
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Replying to @stephentyrone @oshepherd and
(FFS people, when you design an ISA, put CLZ in. The fact that you never see it in high-level languages does not mean it’s not necessary.)
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Replying to @stephentyrone @oshepherd and
Someone really needs to publish a paper that’s just a list of bad ISA and ABI decisions and why they’re bad and what to do instead.
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Replying to @stephentyrone @hikari_no_yume and
Starting point: * Your ISA should have [R+R<<k] loads/stores * An instruction which can compute A=B+C<<k is incredibly useful * 20-bit branch range is not enough (look at the size of a chromium lib sometime) * Have something like A64 BFM or PPC RLWINM
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Replying to @erincandescent @stephentyrone and
* If you have LL/SC, be prepared to spend the next 10 years expanding the list of "things you can't do in an LL/SC loop"
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riscv solved that by just writing a rule from the start that you can only do a small whitelist of stuff in the ll/sc loop...
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Replying to @RichFelker @oshepherd and
Do they guarantee forward progress for that set of instructions? IIUC most architectures don't, even for the "safe" set.
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