Yeah, that's basically it. Dynamically adjusting delays due to very small timing margin. Note that DRAM training on x86 is...
-
-
Wirth's Law, our insatiable desire for speed, reducing the agonizing slowness of waiting for memory on cache miss.
-
Law of no premature optimization: first make it work right, then make it fast, but only if you need to.
-
Are you volunteering your skills to go RE MRC/FSP code? :P
-
No, just volunteering unconventional approaches as ideas to crack open the platform. Maybe they're bogus or maybe they inspire someone.
End of conversation
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.