Contents are less exciting though, probably need to go look up NERF docs for interesting stuff. Not so interested in Busybox rewrite in Go..
I'd be happy with c.2000 DRAM performance if it meant you could get by with near-zero need for per-chipset/soc-revision firmware logic.
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so e.g. J-core doesn't need to do any DRAM training, but Intel isn't going to bother with this. Hashtag economics.
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I mean from a standpoint of programming x86 early boot - can you clock dram down there so naive timing params work?
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And what happens after you need to clock it back up to run the OS?
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Why do you need to?
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Wirth's Law, our insatiable desire for speed, reducing the agonizing slowness of waiting for memory on cache miss.
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Law of no premature optimization: first make it work right, then make it fast, but only if you need to.
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Are you volunteering your skills to go RE MRC/FSP code? :P
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No, just volunteering unconventional approaches as ideas to crack open the platform. Maybe they're bogus or maybe they inspire someone.
End of conversation
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