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RichFelker's profile
Rich Felker
Rich Felker
Rich Felker
@RichFelker

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Rich Felker

@RichFelker

Yeah, I do @musllibc, FOSS & infosec stuff. But now is not the time for a mostly-/only-tech Twitter feed.

musl-libc.org
Joined March 2014

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    1. Rich Felker‏ @RichFelker 30 Oct 2017

      Contents are less exciting though, probably need to go look up NERF docs for interesting stuff. Not so interested in Busybox rewrite in Go..

      1 reply 0 retweets 0 likes
      Show this thread
    2. Rich Felker‏ @RichFelker 30 Oct 2017

      During Q&A, interesting claim that first stages are hard to replace due to complex 1B insn "DRAM training" step.

      1 reply 0 retweets 0 likes
      Show this thread
    3. Rich Felker‏ @RichFelker 30 Oct 2017

      Is this specific to latest DDR silliness & dangerous timing margins? Earlier DDR seems relatively easy to drive.

      1 reply 0 retweets 0 likes
      Show this thread
    4. Rich Felker‏ @RichFelker 30 Oct 2017

      This seems related but doesn't help answering "WTF is training?"https://github.com/librecore-org/librecore/wiki/Understanding-DDR-Memory-Training …

      1 reply 0 retweets 1 like
      Show this thread
    5. Robert Ou‏ @rqou_ 30 Oct 2017
      Replying to @RichFelker

      Yeah, that's basically it. Dynamically adjusting delays due to very small timing margin. Note that DRAM training on x86 is...

      2 replies 0 retweets 0 likes
    6. Rich Felker‏ @RichFelker 30 Oct 2017
      Replying to @rqou_

      Is there a reason you can't just set static delays that are a safe margin above any measurement you'd get rather than training?

      1 reply 0 retweets 0 likes
    7. Robert Ou‏ @rqou_ 30 Oct 2017
      Replying to @RichFelker

      That indeed used to be possible, and I've done it for DDR1. But we eventually made trade-offs so that this is now too difficult

      1 reply 0 retweets 0 likes
    8. Robert Ou‏ @rqou_ 30 Oct 2017
      Replying to @rqou_ @RichFelker

      e.g. it turns out that we can get better signal integrity with a "fly-by" signal routing vs a tree. But this means that...

      1 reply 0 retweets 0 likes
    9. Robert Ou‏ @rqou_ 30 Oct 2017
      Replying to @rqou_ @RichFelker

      the data from chip 0 on a DIMM comes out before the data from chip N. Now you need to align the data, and this depends on propagation delays

      1 reply 0 retweets 0 likes
    10. Rich Felker‏ @RichFelker 30 Oct 2017
      Replying to @rqou_

      Is there no way to just turn down the DRAM clock to the point where the propagation delay is negligible?

      2 replies 0 retweets 0 likes
      Rich Felker‏ @RichFelker 30 Oct 2017
      Replying to @RichFelker @rqou_

      I'd be happy with c.2000 DRAM performance if it meant you could get by with near-zero need for per-chipset/soc-revision firmware logic.

      2:17 PM - 30 Oct 2017
      1 reply 0 retweets 0 likes
        1. New conversation
        2. Robert Ou‏ @rqou_ 30 Oct 2017
          Replying to @RichFelker

          so e.g. J-core doesn't need to do any DRAM training, but Intel isn't going to bother with this. Hashtag economics.

          1 reply 0 retweets 0 likes
        3. Rich Felker‏ @RichFelker 30 Oct 2017
          Replying to @rqou_

          I mean from a standpoint of programming x86 early boot - can you clock dram down there so naive timing params work?

          2 replies 0 retweets 0 likes
        4. William D. Jones‏ @cr1901 30 Oct 2017
          Replying to @RichFelker @rqou_

          And what happens after you need to clock it back up to run the OS?

          2 replies 0 retweets 0 likes
        5. Rich Felker‏ @RichFelker 30 Oct 2017
          Replying to @cr1901 @rqou_

          Why do you need to?

          1 reply 0 retweets 0 likes
        6. William D. Jones‏ @cr1901 30 Oct 2017
          Replying to @RichFelker @rqou_

          Wirth's Law, our insatiable desire for speed, reducing the agonizing slowness of waiting for memory on cache miss.

          1 reply 0 retweets 0 likes
        7. Rich Felker‏ @RichFelker 30 Oct 2017
          Replying to @cr1901 @rqou_

          Law of no premature optimization: first make it work right, then make it fast, but only if you need to.

          2 replies 0 retweets 0 likes
        8. Robert Ou‏ @rqou_ 30 Oct 2017
          Replying to @RichFelker @cr1901

          Are you volunteering your skills to go RE MRC/FSP code? :P

          1 reply 0 retweets 0 likes
        9. Rich Felker‏ @RichFelker 30 Oct 2017
          Replying to @rqou_ @cr1901

          No, just volunteering unconventional approaches as ideas to crack open the platform. Maybe they're bogus or maybe they inspire someone.

          0 replies 0 retweets 0 likes
        10. End of conversation

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