seems like something I should have realized sooner: the effective performance range of RISC style ISA's is not particularly variable...
Stupid ABI conventions can often be even more costly than ISA issues though.
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mine now has both PC-relative (via an instr pair) and scaled index/offset, but has seemingly hit a plateau (wrt speed and code density).
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though, I suspect there is still more that can be done with compiler optimizations (given GCC can still achieve better perf than BGBCC).
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I am not so sure if it is most efficiently using the registers; scratch registers aren't really used for variables, but only for temps, ...
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though, as a lame side effect, most of the time the compiler is only using around half the available registers, but reg-alloc has hair...
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some operations, to be performed, need ~ 6 or 7 registers, so any vars in these regs would need to be demand-evicted (w/o needing more regs)
End of conversation
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