The RISC-V processor I'm looking at right now really doesn't like it when one disables compressed ISA using a not-32-bit-aligned opcode..
For virt/priv control, a higher priv domain should perhaps be able to limit features in guest. But never change its own state.
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This is also done with this. There is only one misa CSR, not one per priv level.
Thanks. Twitter will use this to make your timeline better. UndoUndo
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