The RISC-V processor I'm looking at right now really doesn't like it when one disables compressed ISA using a not-32-bit-aligned opcode..
You're comparing the wrong thing. Rv compressed isa isn't gaining perf (except from cache). It's saving size under fixed isa constraint.
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ok. so, perf would then be relative to instr sequences in the 32b ISA, and density would be "how much does the smaller encoding save"?...
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so, very different from, eg, saving space by avoiding constant-loads; or by having a 4B disp16 branch op vs needing 10B for said branch, ...
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looking at RV32 spec, apart from reg-space, nothing obvious jumps out; so would RV also need, eg, ~160-180 MIPs to pull 30fps in Quake?...
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actually; it is looking like, within RISC constraints & w/o enc penalties; similar logic will need similar instr counts indep of ISA?...
End of conversation
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