The RISC-V processor I'm looking at right now really doesn't like it when one disables compressed ISA using a not-32-bit-aligned opcode..
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I see nothing wrong with allowing an implementation to make it writeable. Making it read-only might be the simple fix for this impl.
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It forces either expensive implementation constraints or allowing the existence of "UB". Both seem highly undesirable.
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For virt/priv control, a higher priv domain should perhaps be able to limit features in guest. But never change its own state.
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This is also done with this. There is only one misa CSR, not one per priv level.
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