The RISC-V processor I'm looking at right now really doesn't like it when one disables compressed ISA using a not-32-bit-aligned opcode..
-
-
yeah, didn't as much like Thumb/2 as the coding is pretty messy, but did have some good points. mine, noted, is 16b SH ops w/ 32b escapes...
-
I was more sorta thinking in terms of code density and perf-per-operation, as I haven't exactly gained drastic improvements over SH perf...
-
You're comparing the wrong thing. Rv compressed isa isn't gaining perf (except from cache). It's saving size under fixed isa constraint.
-
ok. so, perf would then be relative to instr sequences in the 32b ISA, and density would be "how much does the smaller encoding save"?...
-
so, very different from, eg, saving space by avoiding constant-loads; or by having a 4B disp16 branch op vs needing 10B for said branch, ...
-
looking at RV32 spec, apart from reg-space, nothing obvious jumps out; so would RV also need, eg, ~160-180 MIPs to pull 30fps in Quake?...
-
actually; it is looking like, within RISC constraints & w/o enc penalties; similar logic will need similar instr counts indep of ISA?...
End of conversation
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.