idle: a 32kHz block-audio buffer will convert from 22kHz PCM, as 11 to 16 samples, w/ an 0.23% drop in playback speed. seems acceptable.
No, just make them deal with a DMA controller that, from the outside, looks like a dumb uC core repeatedly doing MMIO on them.
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Of course you can actually implement the DMAC as a uC core running a polling loop and doing MMIO, but it's more efficient not to. :-)
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it is still a bit of an open issue if I will be able to fit all this into a 25k cell FPGA; may need something bigger (thus, more expensive).
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side note: my current working goal is basically, something that could run Quake, but fitting into a moderately lower-end FPGA.
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Integrating the DMAC with DRAM/CPU cache interfaces may still be significant work but it's one-time not per-peripheral.
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ok, makes sense, may do this eventually. as-is, have both audio and display to deal with (display would need to send 16 scanlines per ISR).
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