Cold boot Linux in 1 clock cycle.https://twitter.com/oe1cxw/status/898687277609566208 …
You're missing the implied context which is soc-on-fpga. Of course it requires nv fpga, not loading bitstream from spi flash.
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Even a SoC on an NV FPGA might have to do DDR SDRAM PHY training.
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At cycle 0 it's running from cache. May have cache stall on first ddr access.
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Fine, you win :P
End of conversation
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