"1 clock cycle" unfortunately can't work in reality because of various phy link training operations used in modern systems
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You're missing the implied context which is soc-on-fpga. Of course it requires nv fpga, not loading bitstream from spi flash.
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Even a SoC on an NV FPGA might have to do DDR SDRAM PHY training.
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At cycle 0 it's running from cache. May have cache stall on first ddr access.
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Fine, you win :P
End of conversation
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Define "cold boot". Resume from suspend/snapshot, maybe.
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Cold = initially no power supplied. It's a physical criterion not a sw arch (trad. booting vs "resuming") one.
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I've had a todo item forever to feed a Linux ROM image to qemu with 256k ram and get it to run it.
End of conversation
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Is it still a cold boot if you're using Optane (or other NV storage) as system memory?
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