@rqou_ "yosys's verilog frontend accepts all kinds of bullshit that's invalid"
Luckily there is its sourcecode for everyone to improve it.
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emacs versus vi is where we came from, but it seems as we as real nerds advanced to fight over VHDL versus Verilog ;-)
Thanks. Twitter will use this to make your timeline better. UndoUndo
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I will not rest until everyone is using ABEL and TECO, and I will achieve this by "winning" arguments on the internet !!!!11eleven
Thanks. Twitter will use this to make your timeline better. UndoUndo
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