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RichFelker's profile
Rich Felker
Rich Felker
Rich Felker
@RichFelker

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Rich Felker

@RichFelker

Yeah, I do @musllibc, FOSS & infosec stuff. But now is not the time for a mostly-/only-tech Twitter feed.

musl-libc.org
Joined March 2014

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    1. whitequark‏ @whitequark 29 Apr 2017
      Replying to @whitequark

      the helpful diagram they made is inverted. they drew it like the written value is a mask but the address is the mask do you hate developers

      1 reply 0 retweets 11 likes
    2. new299‏ @new299 29 Apr 2017
      Replying to @whitequark

      It's not that they hate developers, it's just that they don't think about them at all.

      1 reply 0 retweets 4 likes
    3. Rich Felker‏ @RichFelker 29 Apr 2017
      Replying to @new299 @whitequark

      On the contrary it seems they actually DID think about developers, and the fact that independent code needs to be able to access gpio bits.

      1 reply 0 retweets 0 likes
    4. Rich Felker‏ @RichFelker 29 Apr 2017
      Replying to @RichFelker @new299 @whitequark

      Without such a scheme, you need all access to gpio mediated through a gpio driver that ensures drivers don't clobber each other's changes.

      2 replies 0 retweets 0 likes
    5. William D. Jones‏ @cr1901 29 Apr 2017
      Replying to @RichFelker @new299 @whitequark

      I don't see how this prevents clobbering when "threads" won't know of each other's writes.

      1 reply 0 retweets 0 likes
    6. Rich Felker‏ @RichFelker 29 Apr 2017
      Replying to @cr1901 @new299 @whitequark

      It's assuming each driver does its own synchronization with itself or is single-threaded; that's trivial to satisfy.

      2 replies 0 retweets 0 likes
    7. William D. Jones‏ @cr1901 29 Apr 2017
      Replying to @RichFelker

      What does "it's" in "It's assuming" referring to. Unfortunately I'm lost now :(.

      1 reply 0 retweets 0 likes
    8. Rich Felker‏ @RichFelker 29 Apr 2017
      Replying to @cr1901

      It = my tweet/my point.

      1 reply 0 retweets 0 likes
    9. William D. Jones‏ @cr1901 29 Apr 2017
      Replying to @RichFelker

      Well two drivers (I hope!) aren't going to use the same GPIO line to send/recv data simultaneously, so I don't understand >>

      1 reply 0 retweets 0 likes
    10. William D. Jones‏ @cr1901 29 Apr 2017
      Replying to @cr1901 @RichFelker

      why this is a problem as long as each driver shifts GPIO locations to be changed/masks to the correct positions before writing.

      1 reply 0 retweets 0 likes
      Rich Felker‏ @RichFelker 29 Apr 2017
      Replying to @cr1901

      A single mmio address hosts multiple (up to 32) gpio lines.

      1:10 PM - 29 Apr 2017
      1 reply 0 retweets 0 likes
        1. New conversation
        2. William D. Jones‏ @cr1901 29 Apr 2017
          Replying to @RichFelker

          So each driver reserves a chunk of those lines ahead of time, and every time a write is required, shift to the appriopriate >>

          1 reply 0 retweets 0 likes
        3. William D. Jones‏ @cr1901 29 Apr 2017
          Replying to @cr1901 @RichFelker

          GPIO lines to modify, then send a mask for the other lines to NOT modify them... oh, wait... that's not atomic

          1 reply 0 retweets 0 likes
        4. William D. Jones‏ @cr1901 29 Apr 2017
          Replying to @cr1901 @RichFelker

          (why is it called "RMW" in the case where you send the mask at the same time? From the hardware POV, we're >>

          1 reply 0 retweets 0 likes
        5. William D. Jones‏ @cr1901 29 Apr 2017
          Replying to @cr1901 @RichFelker

          doing a simultaneous W *and* mask at the same time in silicon. There's no intermediate read/modify.)

          0 replies 0 retweets 0 likes
        6. End of conversation

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