the helpful diagram they made is inverted. they drew it like the written value is a mask but the address is the mask do you hate developers
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So each driver reserves a chunk of those lines ahead of time, and every time a write is required, shift to the appriopriate >>
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GPIO lines to modify, then send a mask for the other lines to NOT modify them... oh, wait... that's not atomic
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(why is it called "RMW" in the case where you send the mask at the same time? From the hardware POV, we're >>
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doing a simultaneous W *and* mask at the same time in silicon. There's no intermediate read/modify.)
End of conversation
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