a) not really helping b) your own register definition files place GPIO_DATA 0x3FC past its actual position in memory whypic.twitter.com/RPA1iwNlSk
Yeah, I do @musllibc, FOSS & infosec stuff. But now is not the time for a mostly-/only-tech Twitter feed.
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a) not really helping b) your own register definition files place GPIO_DATA 0x3FC past its actual position in memory whypic.twitter.com/RPA1iwNlSk
oh I see, the idea is that by placing GPIO_DATA at 0x3FC you get a mask of 0xFF, which effectively makes it a boring old GPIO state register
the helpful diagram they made is inverted. they drew it like the written value is a mask but the address is the mask do you hate developers
It's not that they hate developers, it's just that they don't think about them at all.
On the contrary it seems they actually DID think about developers, and the fact that independent code needs to be able to access gpio bits.
Without such a scheme, you need all access to gpio mediated through a gpio driver that ensures drivers don't clobber each other's changes.
or you could just do it like STM32 and have a bitbanding region that provides atomic RMW for every peripheral
Yes, that's a very nice interface from the programming side, but it probably doesn't scale or factor well on the hardware side.
I think I'd prefer hw designs where the cpu's atomics don't have to interact with anything except cache/dram controller. No "bus locks".
Yeah, I don't think bitbanding works on multicore, but *also* I don't think there are Cortex-Ms that don't have exclusive access to periph.
Yes, of course for single-core you have a cheap, trivial global lock you can use: interrupt masking.
But that increases your interrupt latency and pessimizes bitbanging loops.
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