every new uC family I touch has an increasingly more contrived way of operating GPIOs. in 2022 I expect to have to solve a sudokupic.twitter.com/pxvNYr8KxE
Yeah, I do @musllibc, FOSS & infosec stuff. But now is not the time for a mostly-/only-tech Twitter feed.
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every new uC family I touch has an increasingly more contrived way of operating GPIOs. in 2022 I expect to have to solve a sudokupic.twitter.com/pxvNYr8KxE
a) not really helping b) your own register definition files place GPIO_DATA 0x3FC past its actual position in memory whypic.twitter.com/RPA1iwNlSk
oh I see, the idea is that by placing GPIO_DATA at 0x3FC you get a mask of 0xFF, which effectively makes it a boring old GPIO state register
the helpful diagram they made is inverted. they drew it like the written value is a mask but the address is the mask do you hate developers
It's not that they hate developers, it's just that they don't think about them at all.
On the contrary it seems they actually DID think about developers, and the fact that independent code needs to be able to access gpio bits.
Without such a scheme, you need all access to gpio mediated through a gpio driver that ensures drivers don't clobber each other's changes.
I don't see how this prevents clobbering when "threads" won't know of each other's writes.
It's assuming each driver does its own synchronization with itself or is single-threaded; that's trivial to satisfy.
What's nontrivial is synchronizing access to a gpio register between independent drivers that don't know about each other.
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