every new uC family I touch has an increasingly more contrived way of operating GPIOs. in 2022 I expect to have to solve a sudokupic.twitter.com/pxvNYr8KxE
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It's assuming each driver does its own synchronization with itself or is single-threaded; that's trivial to satisfy.
What's nontrivial is synchronizing access to a gpio register between independent drivers that don't know about each other.
What does "it's" in "It's assuming" referring to. Unfortunately I'm lost now :(.
It = my tweet/my point.
Well two drivers (I hope!) aren't going to use the same GPIO line to send/recv data simultaneously, so I don't understand >>
why this is a problem as long as each driver shifts GPIO locations to be changed/masks to the correct positions before writing.
A single mmio address hosts multiple (up to 32) gpio lines.
So each driver reserves a chunk of those lines ahead of time, and every time a write is required, shift to the appriopriate >>
GPIO lines to modify, then send a mask for the other lines to NOT modify them... oh, wait... that's not atomic
(why is it called "RMW" in the case where you send the mask at the same time? From the hardware POV, we're >>
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