every new uC family I touch has an increasingly more contrived way of operating GPIOs. in 2022 I expect to have to solve a sudokupic.twitter.com/pxvNYr8KxE
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Yes, that's a very nice interface from the programming side, but it probably doesn't scale or factor well on the hardware side.
I think I'd prefer hw designs where the cpu's atomics don't have to interact with anything except cache/dram controller. No "bus locks".
Yeah, I don't think bitbanding works on multicore, but *also* I don't think there are Cortex-Ms that don't have exclusive access to periph.
And CPUs other than Cortex-M-class don't really have the address space to spare for bitbanding, so it works out in the end.
fwiw not all Cortex-M have bitbanding. M7 at least does not
I think it's vendor-dependent, at least for AHB/APB peripherals, no?
no, Cortex-M3/M4 implement bitbanding by doing locked RMW ops over AHB. M7 doesn't in part because it moved to AXI
huh, you are right. So TM4C has a bit-banded GPIO peripheral *on top of* the M4 bit-banded area
part of me thinks a good idea would be to move to 16-bit GPIO ports. Upper 16 bits of write data = mask!
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