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RichFelker's profile
Rich Felker
Rich Felker
Rich Felker
@RichFelker

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Rich Felker

@RichFelker

Yeah, I do @musllibc, FOSS & infosec stuff. But now is not the time for a mostly-/only-tech Twitter feed.

musl-libc.org
Joined March 2014

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    1. whitequark‏ @whitequark 29 Apr 2017

      every new uC family I touch has an increasingly more contrived way of operating GPIOs. in 2022 I expect to have to solve a sudokupic.twitter.com/pxvNYr8KxE

      4 replies 15 retweets 54 likes
    2. whitequark‏ @whitequark 29 Apr 2017
      Replying to @whitequark

      a) not really helping b) your own register definition files place GPIO_DATA 0x3FC past its actual position in memory whypic.twitter.com/RPA1iwNlSk

      1 reply 0 retweets 2 likes
    3. whitequark‏ @whitequark 29 Apr 2017
      Replying to @whitequark

      oh I see, the idea is that by placing GPIO_DATA at 0x3FC you get a mask of 0xFF, which effectively makes it a boring old GPIO state register

      3 replies 0 retweets 4 likes
    4. whitequark‏ @whitequark 29 Apr 2017
      Replying to @whitequark

      the helpful diagram they made is inverted. they drew it like the written value is a mask but the address is the mask do you hate developers

      1 reply 0 retweets 11 likes
    5. new299‏ @new299 29 Apr 2017
      Replying to @whitequark

      It's not that they hate developers, it's just that they don't think about them at all.

      1 reply 0 retweets 4 likes
    6. Rich Felker‏ @RichFelker 29 Apr 2017
      Replying to @new299 @whitequark

      On the contrary it seems they actually DID think about developers, and the fact that independent code needs to be able to access gpio bits.

      1 reply 0 retweets 0 likes
    7. Rich Felker‏ @RichFelker 29 Apr 2017
      Replying to @RichFelker @new299 @whitequark

      Without such a scheme, you need all access to gpio mediated through a gpio driver that ensures drivers don't clobber each other's changes.

      2 replies 0 retweets 0 likes
    8. whitequark‏ @whitequark 29 Apr 2017
      Replying to @RichFelker @new299

      or you could just do it like STM32 and have a bitbanding region that provides atomic RMW for every peripheral

      1 reply 0 retweets 2 likes
      Rich Felker‏ @RichFelker 29 Apr 2017
      Replying to @whitequark @new299

      Yes, that's a very nice interface from the programming side, but it probably doesn't scale or factor well on the hardware side.

      12:47 PM - 29 Apr 2017
      1 reply 0 retweets 0 likes
        1. New conversation
        2. Rich Felker‏ @RichFelker 29 Apr 2017
          Replying to @RichFelker @whitequark @new299

          I think I'd prefer hw designs where the cpu's atomics don't have to interact with anything except cache/dram controller. No "bus locks".

          1 reply 0 retweets 0 likes
        3. whitequark‏ @whitequark 29 Apr 2017
          Replying to @RichFelker @new299

          Yeah, I don't think bitbanding works on multicore, but *also* I don't think there are Cortex-Ms that don't have exclusive access to periph.

          3 replies 0 retweets 0 likes
        4. whitequark‏ @whitequark 29 Apr 2017
          Replying to @whitequark @RichFelker @new299

          And CPUs other than Cortex-M-class don't really have the address space to spare for bitbanding, so it works out in the end.

          1 reply 0 retweets 0 likes
        5.  🎃 unsafe { mem::transmute(@erincandescent) }  🎃‏ @erincandescent 29 Apr 2017
          Replying to @whitequark @RichFelker @new299

          fwiw not all Cortex-M have bitbanding. M7 at least does not

          1 reply 0 retweets 0 likes
        6. whitequark‏ @whitequark 29 Apr 2017
          Replying to @erincandescent @oshepherd and

          I think it's vendor-dependent, at least for AHB/APB peripherals, no?

          1 reply 0 retweets 0 likes
        7.  🎃 unsafe { mem::transmute(@erincandescent) }  🎃‏ @erincandescent 29 Apr 2017
          Replying to @whitequark @RichFelker @new299

          no, Cortex-M3/M4 implement bitbanding by doing locked RMW ops over AHB. M7 doesn't in part because it moved to AXI

          1 reply 0 retweets 0 likes
        8. whitequark‏ @whitequark 29 Apr 2017
          Replying to @erincandescent @oshepherd and

          huh, you are right. So TM4C has a bit-banded GPIO peripheral *on top of* the M4 bit-banded area

          1 reply 0 retweets 0 likes
        9.  🎃 unsafe { mem::transmute(@erincandescent) }  🎃‏ @erincandescent 29 Apr 2017
          Replying to @whitequark @RichFelker @new299

          part of me thinks a good idea would be to move to 16-bit GPIO ports. Upper 16 bits of write data = mask!

          1 reply 0 retweets 1 like
        10. 1 more reply

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