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RichFelker's profile
Rich Felker
Rich Felker
Rich Felker
@RichFelker

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Rich Felker

@RichFelker

Yeah, I do @musllibc, FOSS & infosec stuff. But now is not the time for a mostly-/only-tech Twitter feed.

musl-libc.org
Joined March 2014

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    1. Fabian Giesen‏ @rygorous 11 Dec 2016
      Replying to @SebAaltonen

      this is my #1 pet peeve aaarrgh *the key problem with linked lists has nothing to do with cache misses!* (really.)

      1 reply 1 retweet 1 like
    2. Fabian Giesen‏ @rygorous 12 Dec 2016
      Replying to @rygorous @SebAaltonen

      if cache misses were the key problem, "Node *arr[N];" would be equivalent to a N-Node linked list. But it rarely is!

      3 replies 0 retweets 0 likes
    3. Brendan G Bohannon‏ @cr88192 12 Dec 2016
      Replying to @rygorous @SebAaltonen

      access-by-index and swapping items around are bigger issues IMO, faster and easier with arrays than with lists.

      1 reply 0 retweets 0 likes
    4. Sebastian Aaltonen‏ @SebAaltonen 12 Dec 2016
      Replying to @cr88192 @rygorous

      OoO works pretty well with array random access. It can calculate address to and fetch multiple array items concurrently.

      2 replies 0 retweets 0 likes
    5. William D. Jones‏ @cr1901 12 Dec 2016
      Replying to @SebAaltonen @cr88192 @rygorous

      How can OoO fetch multiple items concurrently? I feel like I'm missing something...

      2 replies 0 retweets 0 likes
    6. Fabian Giesen‏ @rygorous 12 Dec 2016
      Replying to @cr1901 @SebAaltonen @cr88192

      "for (i = 0; i < N; ++i) doThing(x[i]);" doThing for i=1 can start before i=0 finishes (if no data deps)

      2 replies 0 retweets 0 likes
    7. Fabian Giesen‏ @rygorous 12 Dec 2016
      Replying to @rygorous @cr1901 and

      in practice it's not rare for the FE to be 3+ iterations ahead in short loops

      2 replies 0 retweets 0 likes
    8. Steve Canon‏ @stephentyrone 12 Dec 2016
      Replying to @rygorous @cr1901 and

      yes! Often hundreds of instructions at a time in some phase of being processed.

      1 reply 0 retweets 0 likes
    9. Brendan G Bohannon‏ @cr88192 12 Dec 2016
      Replying to @stephentyrone @rygorous and

      newer/Intel specific, or also true of mid/late 2000s AMD chips (K9 & K10)?...

      1 reply 0 retweets 0 likes
    10. Fabian Giesen‏ @rygorous 12 Dec 2016
      Replying to @cr88192 @stephentyrone and

      well over 100 instructions in flight is true of current Intel, AMD, and high-end ARM chips.

      2 replies 0 retweets 1 like
      Rich Felker‏ @RichFelker 12 Dec 2016
      Replying to @rygorous @cr88192 and

      How does that avoid P4-era pathologically-bad performance on misses?

      5:32 PM - 12 Dec 2016
      2 replies 0 retweets 0 likes
        1. New conversation
        2. Steve Canon‏ @stephentyrone 12 Dec 2016
          Replying to @RichFelker @rygorous and

          better predictors, better at discarding results without needing to flush everything.

          1 reply 0 retweets 1 like
        3. Steve Canon‏ @stephentyrone 12 Dec 2016
          Replying to @stephentyrone @RichFelker and

          i.e. finer grained tracking of everything. Power/area/complexity cost is worth it.

          2 replies 0 retweets 1 like
        4. Rich Felker‏ @RichFelker 12 Dec 2016
          Replying to @stephentyrone @rygorous and

          Why can't we just use that area for 100x as many super-dumb cores?

          5 replies 0 retweets 0 likes
        5. Fabian Giesen‏ @rygorous 12 Dec 2016
          Replying to @RichFelker @stephentyrone

          Short version is that, even if you have a workload that scales to 100 cores, that's not necessarily a very

          1 reply 0 retweets 0 likes
        6. Fabian Giesen‏ @rygorous 12 Dec 2016
          Replying to @rygorous @RichFelker @stephentyrone

          power-efficient thing to do either. There's structural reasons for why communication within a core is more

          1 reply 0 retweets 0 likes
        7. Fabian Giesen‏ @rygorous 12 Dec 2016
          Replying to @rygorous @RichFelker @stephentyrone

          efficient than between cores. Having lots of small cores work on disjoint data gives good power/perf. If you have

          1 reply 0 retweets 0 likes
        8. Fabian Giesen‏ @rygorous 12 Dec 2016
          Replying to @rygorous @RichFelker @stephentyrone

          that kind of workload. But if there's any potential of sharing or need to communicate, things change.

          1 reply 0 retweets 0 likes
        9. Fabian Giesen‏ @rygorous 12 Dec 2016
          Replying to @rygorous @RichFelker @stephentyrone

          Memory access (and more mem BW) is *crazy* expensive in terms of power. Hence, caches. But caches are only good

          1 reply 0 retweets 0 likes
        10. 13 more replies
        1. New conversation
        2. Brendan G Bohannon‏ @cr88192 12 Dec 2016
          Replying to @RichFelker @rygorous and

          I wonder; in my uses, unpredictable "if()" branches can be very expensive.

          1 reply 0 retweets 0 likes
        3. Brendan G Bohannon‏ @cr88192 12 Dec 2016
          Replying to @cr88192 @RichFelker and

          a lot of "branch free" logic used in perf sensitive code to avoid "eating it"...

          0 replies 0 retweets 0 likes
        4. End of conversation

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