@cr1901 @RichFelker @scanlime But back in reality, reason you need PHY IC is that most IC pins object somewhat mightily to inductive loads
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Replying to @erincandescent
@oshepherd@RichFelker@scanlime From what I can also gather, output of PHY is differential; output from FPGA isn't (without directives).2 replies 0 retweets 0 likes -
Replying to @cr1901
@cr1901@RichFelker@scanlime FPGAs have lots of differential pairs; but their outputs are not powerful or robust enough to drive an xfrmer1 reply 0 retweets 0 likes -
Replying to @erincandescent
@oshepherd@RichFelker@scanlime Then what's the easiest way to add Ethernet to a board that doesn't have it but has lots of GPIO?2 replies 0 retweets 0 likes -
Replying to @cr1901
@cr1901@oshepherd@scanlime Depends on your definition of easiest. If you have HDL code for your own emac, just hook up a simple PHY.1 reply 0 retweets 0 likes -
Replying to @RichFelker
@cr1901@oshepherd@scanlime If not, get a MAC+PHY module that you can interface with; IIRC some work over SPI.2 replies 0 retweets 0 likes -
Replying to @RichFelker
@RichFelker@cr1901@scanlime Over SPI ENC28J60 is common & easy, though only 10BASE-T. Newer ENC* family members do 1001 reply 0 retweets 0 likes -
Replying to @erincandescent
@RichFelker@cr1901@scanlime (though they can't sustain 100mbit/s over SPI)1 reply 0 retweets 0 likes -
Replying to @erincandescent
@oshepherd@cr1901@scanlime When your cpu is clocked at 50 MHz it's hard to make use of 100 Mbit/s anyway.1 reply 0 retweets 0 likes -
Replying to @RichFelker
@RichFelker It's more that I don't want a softcore CPU to waste time trying to send data one byte at a time.1 reply 0 retweets 0 likes
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Replying to @RichFelker
@RichFelker Then I guess there's no problem :P. Need to figure out how I might get ENC* support into Net if it doesn't exist.1 reply 0 retweets 0 likes -
Replying to @cr1901
@RichFelker Btw, if you're wondering why I like Net: 1. A Certain Init System is crap. 2. Portability is awesome :D.0 replies 0 retweets 1 like
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