@scanlime What prevents me from connecting a Magjack breakout to FPGA pins if I implement the link layer on FPGA? The Magjack has the >>
@cr1901 @oshepherd @scanlime If not, get a MAC+PHY module that you can interface with; IIRC some work over SPI.
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@RichFelker@oshepherd SPI slows things down/would prefer not to deal with that. But yes I know of those ENC-series chips.Thanks. Twitter will use this to make your timeline better. UndoUndo
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@RichFelker@cr1901@scanlime Over SPI ENC28J60 is common & easy, though only 10BASE-T. Newer ENC* family members do 100 -
@RichFelker@cr1901@scanlime (though they can't sustain 100mbit/s over SPI) -
@oshepherd@cr1901@scanlime When your cpu is clocked at 50 MHz it's hard to make use of 100 Mbit/s anyway. -
@RichFelker It's more that I don't want a softcore CPU to waste time trying to send data one byte at a time. -
@cr1901 That's why the next update to J-core's SPI controller will have DMA. :-) -
@RichFelker Then I guess there's no problem :P. Need to figure out how I might get ENC* support into Net if it doesn't exist. -
@RichFelker Btw, if you're wondering why I like Net: 1. A Certain Init System is crap. 2. Portability is awesome :D.
End of conversation
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