Looks like all modern memory without ECC is vulnerable to rowhammer: http://arstechnica.com/security/2016/03/once-thought-safe-ddr4-memory-shown-to-be-vulnerable-to-rowhammer/ …
@landley With ECC, too. The only reliable mitigation is drastically increasing refresh rate (decreasing refresh interval).
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@RichFelker or intelligently scheduling refresh based on access patterns and layout. -
@landley That would be possible with an intelligent ddr controller, I think. But not as a mitigation on existing hardware. -
@RichFelker One of the things I want to ask niishi-san about is _what_ DDR jcore supports. 2/3/4, what's the roadmap...
End of conversation
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