Just built my first from-source J2 soc fpga bitstream; up til now I've just been working on the sw side of the project.
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Replying to @RichFelker
Only took 10 min on
@scaleway's 2.4 GHz Atoms; sadly SMP didn't help. This was with the old source release; new with cache will be slower.1 reply 0 retweets 0 likes -
Replying to @RichFelker
Overall it's not a big entry barrier. The Xilinx toolchain crap is the worst part.
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Replying to @RichFelker
It needs a license key despite being no-cost, gui installer and license key setup, and uses pw-protected 7z files to block installer bypass.
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Replying to @RichFelker
@RichFelker is it as automation-hostile as the Altera tools? I could never figure out how to derive a makefile-driven setup with those...1 reply 0 retweets 0 likes -
Replying to @damienmiller
@damienmiller The J-core J2 build system is entirely Makefiles. Only installation of ISE seems to be automation-hostile.1 reply 0 retweets 0 likes -
Replying to @RichFelker
@damienmiller But unless you already know which of the 150+ ISE binaries are the useful (non-IDE-crap) ones, I guess it's hard...1 reply 0 retweets 1 like
@damienmiller Studying the J-core source would be a good way to figure that out. :-)
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Replying to @RichFelker
@RichFelker thanks - I'll take a look the next time I try to use a FPGA for more then self-education0 replies 0 retweets 0 likesThanks. Twitter will use this to make your timeline better. UndoUndo
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