Just built my first from-source J2 soc fpga bitstream; up til now I've just been working on the sw side of the project.
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Replying to @RichFelker
Only took 10 min on
@scaleway's 2.4 GHz Atoms; sadly SMP didn't help. This was with the old source release; new with cache will be slower.1 reply 0 retweets 0 likes -
Replying to @RichFelker
Overall it's not a big entry barrier. The Xilinx toolchain crap is the worst part.
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Replying to @RichFelker
@RichFelker Yeah getting ICE up and running is painful just because of the sheer size and complexity. Where's the easy mode version. :)1 reply 0 retweets 0 likes -
Replying to @RichFelker
@RichFelker too bad they treat the bitstream format as some kind of crazy super secret that's vital for their continued success.2 replies 0 retweets 0 likes -
Replying to @dotstdy
@dotstdy On that topic, this SE answer and the linked PDF file are somewhat informative: http://reverseengineering.stackexchange.com/a/86/156771 reply 0 retweets 0 likes
@dotstdy I think someone with the time and motivation could pretty easily RE the bitstream format knowing what the basic blocks look like.
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