Just built my first from-source J2 soc fpga bitstream; up til now I've just been working on the sw side of the project.
Overall it's not a big entry barrier. The Xilinx toolchain crap is the worst part.
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It needs a license key despite being no-cost, gui installer and license key setup, and uses pw-protected 7z files to block installer bypass.
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@RichFelker is it as automation-hostile as the Altera tools? I could never figure out how to derive a makefile-driven setup with those... -
@damienmiller The J-core J2 build system is entirely Makefiles. Only installation of ISE seems to be automation-hostile. -
@damienmiller But unless you already know which of the 150+ ISE binaries are the useful (non-IDE-crap) ones, I guess it's hard... -
@damienmiller Studying the J-core source would be a good way to figure that out. :-) -
@RichFelker thanks - I'll take a look the next time I try to use a FPGA for more then self-education
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@RichFelker Yeah getting ICE up and running is painful just because of the sheer size and complexity. Where's the easy mode version. :) -
@dotstdy In theory you could strip down the download and install if you extract the 7z passwords. But in the long term we need FOSS tools. -
@RichFelker too bad they treat the bitstream format as some kind of crazy super secret that's vital for their continued success. -
@dotstdy On that topic, this SE answer and the linked PDF file are somewhat informative: http://reverseengineering.stackexchange.com/a/86/15677 -
@dotstdy I think someone with the time and motivation could pretty easily RE the bitstream format knowing what the basic blocks look like.
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