So apparently MIPS R6 is a new ISA that's not even backwards compatible with previous MIPS ISA levels. Can anyone confirm?
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@cr1901 Neither has viable real hardware yet, though. -
@RichFelker I can live with FPGA impls for now. Even w/ real ASIC impls, it's not going to be easy to use in hobbyist projects :(. -
@RichFelker I can't SMD solder well. I can pay companies to do it for me after I make a PCB design. Guess how many PCBs I made w/o mistakes? -
@RichFelker (Zero. Exactly zero. I have yet to make a PCB where I didn't find a mistake after they came back from the fab.) -
@cr1901 This is why it's not viable. Their academics are too busy making theoretical optimized designs, ignoring need to make _boards_. -
@RichFelker@cr1901 it takes time, there's not really a way around that -
@asbradbury@cr1901 Even if it were expensive & suboptimal, having a working board would rapidly accelerate adoption/development.
End of conversation
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@RichFelker@risc_v I have found or1k Verilog code to be very difficult to read. However, I should try again to see if that was just a fluke -
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