Interesting find: the "Peterson lock" described here has much lower failure rate than "Dekker" on x86 w/out barrier:http://bartoszmilewski.com/2008/11/05/who-ordered-memory-fences-on-an-x86/ …
@cr1901 Producing a compiler that could support such an arch would be extremely difficult, probably requires inserting barriers everywhere.
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@RichFelker The only reason I can think of even wanting an arch like that is to keep throughput high w/ less silicon used. >> -
@RichFelker That said, it would be extremely crappy if reordering like that was possible on a single core.
End of conversation
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