Trying to learn to read vhdl. >_<
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Replying to @RichFelker
@RichFelker have you considered learning Chisel? https://chisel.eecs.berkeley.edu/ – a higher level HDL that generates Verilog@risc_v1 reply 0 retweets 0 likes -
Replying to @RichFelker
@RichFelker@risc_v Understand. BTW plugged musl about a week before the glibc disclosure (i'm not on vendor sec) https://listmaster.pepperfish.net/pipermail/lowrisc-dev-lists.lowrisc.org/2016-February/000270.html …1 reply 0 retweets 1 like
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