@RichFelker have you considered learning Chisel? https://chisel.eecs.berkeley.edu/ – a higher level HDL that generates Verilog @risc_v
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@mjcmeta
@risc_v The key word is read. Your question is like asking someone trying to learn to read French if they tried to learn German :-) -
@RichFelker@risc_v Understand. BTW plugged musl about a week before the glibc disclosure (i'm not on vendor sec) https://listmaster.pepperfish.net/pipermail/lowrisc-dev-lists.lowrisc.org/2016-February/000270.html … -
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@RichFelker This was inevitable. -
@landley And it's way easier than I expected. This syntax reference was a lot more helpful to me than tutorials: https://webdocs.cs.ualberta.ca/~amaral/courses/329/labs/VHDL_Reference.html … -
@landley It quickly got me up to the level of being able to devise a hack that makes things work. -
@RichFelker I think VHDL will be fascinating. And then I'll dig into the j-core source, and I do NOT have time for another time sink now. :)
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@richfelker At Least It’s Not Verilog(tm)Thanks. Twitter will use this to make your timeline better. UndoUndo
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@RichFelker one doesn't read vhdl, one just comprehends it.Thanks. Twitter will use this to make your timeline better. UndoUndo
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@RichFelker It's quite a fun programming model.Thanks. Twitter will use this to make your timeline better. UndoUndo
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@RichFelker I'm sorry for you. Btw, remember that it's case insensitive. ALL THOSE CAPS are just convention.Thanks. Twitter will use this to make your timeline better. UndoUndo
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@RichFelker My sincere sympathies. Both VHDL and Verilog are easier to read than write IME. I use Python => Verilog translation.Thanks. Twitter will use this to make your timeline better. UndoUndo
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