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RichFelker's profile
Rich Felker
Rich Felker
Rich Felker
@RichFelker

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Rich Felker

@RichFelker

Yeah, I do @musllibc, FOSS & infosec stuff. But now is not the time for a mostly-/only-tech Twitter feed.

musl-libc.org
Joined March 2014

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    Rich Felker‏ @RichFelker 10 Mar 2016

    Trying to learn to read vhdl. >_<

    7:17 PM - 10 Mar 2016
    • 1 Retweet
    • 2 Likes
    • Philip Gleo Ian Hansen mork 👽
    7 replies 1 retweet 2 likes
      1. New conversation
      2. mork  👽‏ @corkmork 10 Mar 2016
        Replying to @RichFelker

        @RichFelker have you considered learning Chisel? https://chisel.eecs.berkeley.edu/  – a higher level HDL that generates Verilog @risc_v

        1 reply 0 retweets 0 likes
      3. Rich Felker‏ @RichFelker 10 Mar 2016
        Replying to @corkmork

        @mjcmeta @risc_v The key word is read. Your question is like asking someone trying to learn to read French if they tried to learn German :-)

        2 replies 0 retweets 1 like
      4. mork  👽‏ @corkmork 10 Mar 2016
        Replying to @RichFelker

        @RichFelker @risc_v Understand. BTW plugged musl about a week before the glibc disclosure (i'm not on vendor sec) https://listmaster.pepperfish.net/pipermail/lowrisc-dev-lists.lowrisc.org/2016-February/000270.html …

        1 reply 0 retweets 1 like
      5. Rich Felker‏ @RichFelker 10 Mar 2016
        Replying to @corkmork

        @mjcmeta Porting @musllibc to @risc_v is a proposed GSoC project under @lowRISC, but one interested student already has a lot of progress.

        1 reply 1 retweet 1 like
      6. Rich Felker‏ @RichFelker 10 Mar 2016
        Replying to @RichFelker

        @mjcmeta I'd really love to end up with a project that has @risc_v as a polished first-class supported arch for @musllibc once it's done.

        0 replies 0 retweets 1 like
      7. End of conversation
      1. New conversation
      2. @landley‏ @landley 10 Mar 2016
        Replying to @RichFelker

        @RichFelker This was inevitable.

        1 reply 0 retweets 0 likes
      3. Rich Felker‏ @RichFelker 10 Mar 2016
        Replying to @landley

        @landley And it's way easier than I expected. This syntax reference was a lot more helpful to me than tutorials: https://webdocs.cs.ualberta.ca/~amaral/courses/329/labs/VHDL_Reference.html …

        1 reply 0 retweets 0 likes
      4. Rich Felker‏ @RichFelker 10 Mar 2016
        Replying to @RichFelker

        @landley It quickly got me up to the level of being able to devise a hack that makes things work.

        1 reply 0 retweets 0 likes
      5. @landley‏ @landley 10 Mar 2016
        Replying to @RichFelker

        @RichFelker I think VHDL will be fascinating. And then I'll dig into the j-core source, and I do NOT have time for another time sink now. :)

        0 replies 0 retweets 0 likes
      6. End of conversation
      1. Shiz‏ @dev_console 10 Mar 2016
        Replying to @RichFelker

        @richfelker At Least It’s Not Verilog(tm)

        0 replies 0 retweets 0 likes
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      1. Ian Hansen‏ @supershabam 10 Mar 2016
        Replying to @RichFelker

        @RichFelker one doesn't read vhdl, one just comprehends it.

        0 replies 0 retweets 0 likes
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      1. Josh Simmons‏ @dotstdy 10 Mar 2016
        Replying to @RichFelker

        @RichFelker It's quite a fun programming model.

        0 replies 0 retweets 0 likes
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      1. Joachim Strömbergson‏ @Kryptoblog 10 Mar 2016
        Replying to @RichFelker

        @RichFelker I'm sorry for you. Btw, remember that it's case insensitive. ALL THOSE CAPS are just convention.

        0 replies 0 retweets 0 likes
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      1. William D. Jones‏ @cr1901 10 Mar 2016
        Replying to @RichFelker

        @RichFelker My sincere sympathies. Both VHDL and Verilog are easier to read than write IME. I use Python => Verilog translation.

        0 replies 0 retweets 0 likes
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