@laurentbercot @RichFelker can you please provide a benchmark about it? Sounds strange to have such impact...
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Replying to @lu_zero_
@lu_zero_@laurentbercot PIC is historically quite costly on some targets, but better now.3 replies 0 retweets 0 likes -
Replying to @RichFelker
@RichFelker@lu_zero_@laurentbercot It was quite expensive on i386 due to scarce general purpose registers and the poor GCC implementation.1 reply 0 retweets 0 likes -
Replying to @CopperheadOS
@RichFelker@lu_zero_@laurentbercot GCC 5 included substantial PIC optimizations for archs without PIC support: https://software.intel.com/en-us/blogs/2014/12/26/new-optimizations-for-x86-in-upcoming-gcc-50-32bit-pic-mode ….2 replies 1 retweet 0 likes -
Replying to @CopperheadOS
@CopperheadSec@lu_zero_@laurentbercot Without PIC support? Perhaps you mean without efficient PC-relative addressing?1 reply 0 retweets 0 likes -
Replying to @RichFelker
@RichFelker@lu_zero_@laurentbercot Meaning without hardware PIC support like PC relative addressing to make it fast.1 reply 0 retweets 0 likes -
Replying to @CopperheadOS
@RichFelker@lu_zero_@laurentbercot And some have basic PC relative addressing (like 32-bit ARM) but x86_64 / ARMv8 make it nearly free.1 reply 0 retweets 0 likes -
Replying to @CopperheadOS
@RichFelker@lu_zero_@laurentbercot i386 is especially bad because wasting a register is a big deal though. Not as bad to do that on ARM.1 reply 0 retweets 0 likes -
Replying to @CopperheadOS
@CopperheadSec@lu_zero_@laurentbercot ARM doesn't waste a register for PIC (there's no ABI requirement for calling into PLT).1 reply 0 retweets 0 likes -
Replying to @RichFelker
@RichFelker@lu_zero_@laurentbercot Ah, didn't realize that.1 reply 0 retweets 0 likes
@CopperheadSec @lu_zero_ @laurentbercot They have an inter-procedural temp register (ip) that PLT thunks and distant-call-thunks can use.
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