Possible post-Spectre machine architecture: no caches, no DRAM on main bus. A few tens to hundreds of MB of SRAM as the whole physical address space. Large swap on DRAM or SSD, controlled entirely by the OS, to replace flaky, leaky, immutable cache designs.
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Bonus: MMU only needs a small number of physical address bits and doesn't have to interact with any caches.
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Could have i-cache still to avoid contention with data loads/stores, or the MMU could just have separate i-TLB entries with software expected to resolve to separate SRAM banks (duplicating r+x pages in two places), or...
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Just have enough SRAM banks, and distribute address mappings across them such, that it's unlikely for insn fetch and load/store unit to contend for the same bank.
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One thing that's hard is SMP: without a cache and associated coherency protocol, you either have all cores serialized on accessing the same SRAM, or you have to go full NUMA (core-local SRAM) with kernel mediating sharing (essentially rwlock on page backings).
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Replying to @RichFelker
Cpu cache coherence is just a message passing system. Idly wonder if this is mostly a programming language/operating environments issue
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It can all be done at the OS level by ensuring that at all times, for any virtual page, either only one core has a mapping of it, or all cores' mappings are read-only.
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