Possible post-Spectre machine architecture: no caches, no DRAM on main bus. A few tens to hundreds of MB of SRAM as the whole physical address space. Large swap on DRAM or SSD, controlled entirely by the OS, to replace flaky, leaky, immutable cache designs.
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Just have enough SRAM banks, and distribute address mappings across them such, that it's unlikely for insn fetch and load/store unit to contend for the same bank.
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One thing that's hard is SMP: without a cache and associated coherency protocol, you either have all cores serialized on accessing the same SRAM, or you have to go full NUMA (core-local SRAM) with kernel mediating sharing (essentially rwlock on page backings).
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