Possible post-Spectre machine architecture: no caches, no DRAM on main bus. A few tens to hundreds of MB of SRAM as the whole physical address space. Large swap on DRAM or SSD, controlled entirely by the OS, to replace flaky, leaky, immutable cache designs.
-
-
Could have i-cache still to avoid contention with data loads/stores, or the MMU could just have separate i-TLB entries with software expected to resolve to separate SRAM banks (duplicating r+x pages in two places), or...
Show this thread -
Just have enough SRAM banks, and distribute address mappings across them such, that it's unlikely for insn fetch and load/store unit to contend for the same bank.
Show this thread -
One thing that's hard is SMP: without a cache and associated coherency protocol, you either have all cores serialized on accessing the same SRAM, or you have to go full NUMA (core-local SRAM) with kernel mediating sharing (essentially rwlock on page backings).
Show this thread
End of conversation
New conversation -
-
-
As I understand it, Intel's Octane may have a part to play here.
Thanks. Twitter will use this to make your timeline better. UndoUndo
-
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.