Anyone want to place bets on whether the first actual fix for Spectre will be via reverse engineered and patched microcode?https://twitter.com/thorstenholz/status/1031839729145311232 …
Yeah, I do @musllibc, FOSS & infosec stuff. But now is not the time for a mostly-/only-tech Twitter feed.
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Rich Felker Retweeted Thorsten Holz
Anyone want to place bets on whether the first actual fix for Spectre will be via reverse engineered and patched microcode?https://twitter.com/thorstenholz/status/1031839729145311232 …
Rich Felker added,
It can’t be. The problem is C. One must prevent speculation altogether unless one has information on bounds used in speculated branches. mem[__builtin_speculation_safe_value (untrusted)]; Now if the cpu had data about the data dependencies protected (sic) by branches on bounds
The problem is not C, it's speculation. Explicitly marking up sensitive data rather than having the cpu do its job and enforce its contractual protections does not scale and is a losing battle before you even start.
It’s the interface between C and the CPU. Manages languages that have array bounds like C# would be able to express the dependencies required without hand sprinkled speculation barriers. So it is partly C. Ya ideally CPU can not evict based on speculation. Transactional caches.
No. The array bounds are not the range of what's safe to leak. ANY array element except the one the code semantically is supposed to read is not safe to leak.
Consider an emulator written in whatever language with fancy array bounds you like, emulating a machine running untrusted code in multiple privilege domains. Data is all just one big array, bounds do nothing.
I like the idea of a randomised ISA so that payloads need to first crack a high entropy dynamically randomised ISA. Google “crypto binary translation”
This has no relevance to the topic at hand because the attack code doesn't have any relation to the host ISA and no need to know anything about the host running the emulator.
We can also solve L1TF with shadow paging. This was the original rationale for the work on the rv8 JIT engine. Use RISC-V as the IR for dynamic runtime translation/obfuscation with multiple entropy vectors. RISC via CISC to a microop backend. It is however a bit of a pipe dream.
Do you mean Foreshadow? AIUI it's solvable just by not putting data in the unused private bits of not-present PTEs.
But given how awful Intel's been I'd be tempted just to not use PTEs at all, TLBs only, faulting on every miss.
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