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RichFelker's profile
Rich Felker
Rich Felker
Rich Felker
@RichFelker

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Rich Felker

@RichFelker

Yeah, I do @musllibc, FOSS & infosec stuff. But now is not the time for a mostly-/only-tech Twitter feed.

musl-libc.org
Joined March 2014

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    1. Joseph Cox‏ @josephfcox Aug 6

      Spectre/Meltdown nominated for most over hyped bug at Pwnies 😈pic.twitter.com/TVJ8OXXFRy

      5 replies 43 retweets 98 likes
      Show this thread
    2. Rich Felker‏ @RichFelker Aug 6
      Replying to @josephfcox @matthew_d_green

      I want to nominate Spectre for most underhyped, to the point the vendors don't even see it meriting a fix...

      1 reply 0 retweets 1 like
    3. mork  👽‏ @corkmork Aug 6
      Replying to @RichFelker @josephfcox @matthew_d_green

      The chip vendors are adding speculation barriers, but the big problem is adding the required compiler analysis to figure out where to insert them. Requiring users to strategically sprinkle __builtin_speculation_safe_value (untrusted) around code is not an ideal approach.

      1 reply 0 retweets 0 likes
    4. Rich Felker‏ @RichFelker Aug 6
      Replying to @corkmork @josephfcox @matthew_d_green

      That's not a fix. That's a pathetic tool for minimal workarounds on a case-by-case basis. A fix is an MSR to disable speculative execution across branches or entirely.

      1 reply 0 retweets 0 likes
    5. mork  👽‏ @corkmork Aug 6
      Replying to @RichFelker @josephfcox @matthew_d_green

      That’s what is being proposed. BTW Disabling all speculation is a big sledgehammer when it is possible to design CPUs that speculate without visible side effects.

      1 reply 0 retweets 0 likes
      Rich Felker‏ @RichFelker Aug 6
      Replying to @corkmork @josephfcox @matthew_d_green

      I believe it's plausible to design a CPU that speculates without visible side effects, but it sounds difficult. I don't believe it's possible to add that via microcode. An MSR to disable all speculation should be possible as a microcode update.

      8:38 AM - 6 Aug 2018
      5 replies 0 retweets 0 likes
        1. New conversation
        2. mork  👽‏ @corkmork Aug 6
          Replying to @RichFelker @josephfcox @matthew_d_green

          and I believe even that approach needs microcode update; over CPU vendors are proposing other mechanisms to introduce these “speculation barriers”. If it were easy it would be easily fixed. There needs to be fundamental design changes for side-effect free speculation.

          1 reply 0 retweets 1 like
        3. Rich Felker‏ @RichFelker Aug 6
          Replying to @corkmork @josephfcox @matthew_d_green

          Fundamental design changes are needed to make it fast, specifically fast enough to be acceptable to most users. Just fixing it is trivial: nuke speculation.

          2 replies 0 retweets 0 likes
        4. mork  👽‏ @corkmork Aug 6
          Replying to @RichFelker @josephfcox @matthew_d_green

          Nuking speculation is only trivial if that is already “designed in”. Perhaps okay for new processors. The “speculation barrier” is what is on the table for current designs that may be able to be introduced by micro-code.

          1 reply 0 retweets 0 likes
        5. Rich Felker‏ @RichFelker Aug 6
          Replying to @corkmork @josephfcox @matthew_d_green

          Nuking (all, not just BTB) branch prediction should also work (aside from meltdown I'm not aware of other ways speculation could be exploited, but not 100% sure) and seems likely to be possible with microcode.

          1 reply 0 retweets 0 likes
        6. Rich Felker‏ @RichFelker Aug 6
          Replying to @RichFelker @corkmork and

          If neither is possible, vendors should be offering compelling technical explanations of why it's not possible rather than refusing to even speak about it. The appearance is that they DON'T WANT TO FIX IT in any way that would look bad wrt performance.

          0 replies 0 retweets 0 likes
        7. End of conversation
        1. Rich Felker‏ @RichFelker Aug 6
          Replying to @RichFelker @corkmork and

          Old P5 and maybe early P6/ppro era chips had an MSR to disable branch prediction, which would also be likely to suffice if made available again.

          0 replies 0 retweets 0 likes
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        2. mork  👽‏ @corkmork Aug 6
          Replying to @RichFelker @josephfcox @matthew_d_green

          The current proposed fix is to add a “speculation barrier” instruction which needs to be explicitly inserted before vulnerable code (LFENCE on x86); which in itself is a very hard problem that requires alias analysis and proving bounds e.g. hard to do with a language like C.

          1 reply 0 retweets 0 likes
        3. Rich Felker‏ @RichFelker Aug 6
          Replying to @corkmork @josephfcox @matthew_d_green

          This is insufficient and not a fix. ALL CODE is potentially sensitive/vulnerable. Spectre does not require a victim process with a JIT/VM running untrusted code; that's just the easiest vector. Some "pure-data" vectors are known and they will continue to emerge, forever.

          0 replies 0 retweets 1 like
        4. End of conversation
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        2. mork  👽‏ @corkmork Aug 6
          Replying to @RichFelker @josephfcox @matthew_d_green

          It likely may not be or it would have been done. Speculation is on the fast path. It’s a fundamental design issue. It’s possible to do whatever was previously baked in for access via micro-code. e.g. expensive things like flushing the BTB.

          1 reply 0 retweets 0 likes
        3. Rich Felker‏ @RichFelker Aug 6
          Replying to @corkmork @josephfcox @matthew_d_green

          I think you're missing the obvious motivation not to: Intel doesn't want to ship a security feature that makes their chip 75% slower or worse.

          0 replies 0 retweets 0 likes
        4. End of conversation
        1. mork  👽‏ @corkmork Aug 6
          Replying to @RichFelker @josephfcox @matthew_d_green

          Indeed it is plausible to design a CPU that speculates without visible cache side effects, but it requires some very fundamental changes such as changes to caches and cache coherence protocols. Doing so while maintaining similar performance to existing designs is a hard problem.

          0 replies 0 retweets 0 likes
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