Supposedly the actual history of how Intel's hideous segmented design was invented and pushed as a "feature" by hardware engineers:https://retrocomputing.stackexchange.com/a/6989/2070
In any case, designing the whole memory architecture around an efficiency hack for a very specific size range of programs was a ridiculous idea.
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I'd agree, but I still don't believe that's what happened. I'm pretty sure the segment/paragraph hardware was cast in silicon before anyone gave much thought to how programs larger than 64K should be structured for it.
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The 8086 was intended to be an improvement over the 8080/8085, but it was primarily intended for embedded systems. It wasn't expected to dominate the general-purpose computer industry. The iAPX 432 was supposed to do that.
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There is _so_ little information online about iAPX 432 and spiritual successor Rekursiv. From the little I know about them, they both support hardware GC and hardware-OOP. With little information available about "how is this feasible?"...
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The 432 hardware provided relatively little support for OOP in the modern sense. In particular, there was no hardware support for inheritance (method dispatch, vtables).
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The 432 GC support was really just a matter of maintaining three possible colors for each object, to support a mark/sweep collector in software. By having three colors rather than two, it supported Dijlstra's parallel GC, so with at least two CPUs, ...
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... doing a GC didn't have to stop the system.
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The major benefit of the 432 architecture, IMO, was that it was capability-based. A capability is basically an object pointer with embedded permissions. It was not possible to forge capabilities, or to access memory without a capability.
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There was, eg., no way to access memory based on an address. To access anything in memory, you had to have an Access Descriptor (capability) referencing a memory segment, and the offset with the segment.
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As an old IBM PC collector: segmentation bytes (pun intended).
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