OK: So figured out a way to do an accurate FDIV in Verilog; just sort of rig the multiplier to feed back into itself until the reciprocal stabilizes (via Newton-Raphson); then switch over to multiplying the quotient by the newly computed reciprocal...
Uhg, did the Itanic really have that wacky 17-bit-exponent, only-in-register-intermediates format? If so it was probably impossible to do any IEEE arithmetic with its fpu...