OK: So figured out a way to do an accurate FDIV in Verilog; just sort of rig the multiplier to feed back into itself until the reciprocal stabilizes (via Newton-Raphson); then switch over to multiplying the quotient by the newly computed reciprocal...
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It will be exact for 32-bit floats, but there is currently still "noise" in the low-order bits for double-precision values (for both FMUL and FDIV). Still an improvement over my prior attempts, as it passes timing at 100MHz now, so progress I think...
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Basically, FMUL produces a 54-bit intermediate mantissa (via 18-bit muls), but it seems this may not be enough (some stuff "falls off the bottom"). The N-R process also can't reliably converge on an exact result in this case, so a few more bits are lost.
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Correct implementations are possible. https://projects.ncsu.edu/wcae/ISCA2004/submissions/cornea.pdf …
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FWIW: Newton-Raphson can do DIV/SQRT accurate to the available numeric precision; but has the drawback of not being the fastest option around (iterative). OTOH: lookup-table based options can be faster, but precision depends on table size (a limiting factor here), ...
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