lol why is there a bench seat in this supercomputer roomhttps://twitter.com/doctorow/status/1008408947882151938 …
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IIRC, the emitter coupled logic used by the CRAY-1 relied on differential signalling and, as such, the pairs had to be length matched for signal integrity.
i.e. it’d be *very* easy to end up with bit skew on a wide parallel bus of the kind that’s almost certainly present there.
Yep. Propagation speed in wire is complicated (depends on the kind of wire), but around 5ns/m probably for the wires in a Cray 1. An 80MHz clock gives a 12.5ns cycle time, for comparison.
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