Reconfigure.io

@ReconfigureIO

The next stage in computing power

UK, TX, CA and NYC
Vrijeme pridruživanja: kolovoz 2015.

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  1. proslijedio/la je Tweet
    16. svi 2019.

    Really excited to be able to reveal 's closer collaboration with Google and ETH Zurich. New board members and an exciting development roadmap made possible by the support and funding from Google. Also, we're hiring!

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  2. proslijedio/la je Tweet
    17. svi 2019.

    Just merged x/sys module with latest assembly code and now the GC works! Successfully built go-Jsonnet and a webserver with Echo().

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  3. proslijedio/la je Tweet

    I can’t believe what I’m seeing! While running a facial recognition pilot, one man (understandably imho) covered himself up. The police forced him to show his face (& then fined him for disorderly conduct). This is dangerous & terrifying.

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  4. proslijedio/la je Tweet

    Our FCCM short paper is now on arXiv: Yosys+nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs. David Shah, Eddie Hung, Clifford Wolf, Serge Bazanski, Dan Gisselquist, Miodrag Milanović.

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  5. proslijedio/la je Tweet

    Yo internet nerds! Can you help me find some amazing hardware hacking women or under represented minorities on this site. I know a few I want to find more ;)

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  6. proslijedio/la je Tweet

    Not quite the silver bullet, certainly not yet, in compute. Performance v cost (key driver still post-Moore’s Law) is fast being advanced with hardware such as FPGAS & numerous software/architecture developments. is speaking louder in compute but has a way to go.

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  7. proslijedio/la je Tweet
    24. tra 2019.

    LoFive R1 campaign crossed 50% today! It hasn't gone viral yet so I am thinking of making stretch goals to get more backers. Perhaps unlocking a base board if the campaign reaches 100% within the next 2 weeks.

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  8. proslijedio/la je Tweet
    4. tra 2019.

    You might not be aware, but SymbiFlow can synthesize and capable SoCs today. Participate in - applications close in 5 days so be fast! - and help us open up tooling to accelerate innovation in FPGAs:

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  9. proslijedio/la je Tweet

    I feel like if and want to really shake things up they should apply their usual love of Open Source to FPGA bitstreams and support open synthesis and place+route for their FPGAs. Sure, patents and IP and stuff, but they've a big arsenal to defend against trolls

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  10. proslijedio/la je Tweet

    One-size-fits-all models don’t suit due to horizontal & enhancing/enabling characteristics. Research, government initiatives, collaborations, JV’s, corporate venture, licensing, equity/debt and M&A all need to be considered within a nuanced mix

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  11. proslijedio/la je Tweet
    29. ožu 2019.
    Odgovor korisniku/ci

    And it's all available open-source! You can build your own FPGA and implement your own verilog on it today:

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  12. proslijedio/la je Tweet
    21. ožu 2019.

    Boot SMP Linux on + Ariane🚀! The Princeton Parallel Group and IIS ETH are bringing you the first Linux-booting, open-source RISC-V system that scales from single to manycore. Download 1, 2 and 4-core FPGA bit files here:

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  13. proslijedio/la je Tweet

    Find it hard to keep track of all the great Open Source Silicon events? Don't worry. We have collected them all at First up is followed by Week of Open Source Hardware (WOSH) together with and

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  14. proslijedio/la je Tweet
    14. ožu 2019.

    Microsoft is open sourcing Project Zipline to spur faster implementation in silicon

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  15. proslijedio/la je Tweet
    14. ožu 2019.
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  16. proslijedio/la je Tweet
    18. velj 2019.

    i literally moaned "oh no..." when i read the title of this :(

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  17. proslijedio/la je Tweet
    11. pro 2018.

    Today is the best second Tuesday of the month as we once again bring you the newsletter with the latest news from the buzzing world of free and open source silicon featuring and more

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  18. proslijedio/la je Tweet
    5. pro 2018.
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  19. proslijedio/la je Tweet
    4. pro 2018.

    They've done it. Congrats to portfolio company for the success of their mission. Following ICEYE-X1, the world's first SAR satellite under 100kg in mass, ICEYE-X2's use cases will include flood extent monitoring, vessel detection and field segmentation.

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  20. proslijedio/la je Tweet
    28. stu 2018.

    . has also created a new chip, a “AWS Inferentia,” a latency-sensitive high-throughput processor for inferencing. Supports all major frameworks, can be attached to instances and also available with

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